Methods of Analysis

Nodal analysis solves a circuit by finding the voltage at every non-reference node (with respect to ground). Once you know node voltages, every branch current follows from Ohm's law.

Procedure:

1. Choose a reference node (ground) — typically the one with the most branches. Label its voltage 0.
2. Assign a voltage variable $V_1,V_2,\dots$ to each remaining node.
3. Apply KCL at each non-reference node. For a branch from node $i$ to node $j$ through resistance $R$, the current leaving node $i$ is $(V_i-V_j)/R$.
4. Solve the resulting linear system for $V_1,V_2,\dots$.

By inspection — for a circuit with only resistors and independent current sources, the nodal equations can be written directly as $\mathbf{GV}={\mathbf{I}}_s$, where:

• $G_{kk}$ = sum of conductances connected to node $k$
• $G_{kj}$ = negative of conductance between nodes $k$ and $j$
• $I_{s,k}$ = total current source flowing into node $k$

Nodal is generally easier when there are few nodes relative to branches, or when most sources are current sources.

When an ideal voltage source sits directly between two non-reference nodes, you can't write a standard KCL at either end — the source forces a relationship, not a passive current.

The supernode technique: treat the two nodes plus the voltage source between them as one big 'supernode'. KCL still applies to the boundary — currents into the supernode sum to zero — but you need a constraint equation for the voltage source:

$$V_i-V_j=V_s$$

where $V_s$ is the source voltage (sign per the source's polarity).

Procedure:

1. Identify supernodes (any pair of non-reference nodes joined by an ideal voltage source).
2. Write KCL for each supernode treating the two nodes as one.
3. Add the constraint equation $V_i-V_j=V_s$ for each supernode.
4. Write KCL normally at all other nodes.

If the voltage source is between a non-reference node and ground, it's even simpler — that node's voltage is *known* directly ($V_k=V_s$), so it doesn't need a KCL equation.

Mesh analysis solves a circuit by assigning a current variable to each mesh (the smallest closed loops, like window panes in a planar circuit) and applying KVL around each.

Procedure:

1. Identify the meshes. A planar circuit with $b$ branches and $n$ nodes has $\ell =b-n+1$ meshes.
2. Assign a mesh current $i_1,i_2,\dots ,i_{\ell }$ to each, all in the same direction (clockwise by convention).
3. Write KVL around each mesh. For a resistor shared between two meshes, the actual current is the *difference* of the two mesh currents — be careful with signs.
4. Solve the linear system for $i_1,i_2,\dots ,i_{\ell }$.

Branch current through a shared element: if mesh 1 and mesh 2 both flow clockwise and share resistor $R$, then the branch current through $R$ from mesh 1's side is $i_1-i_2$.

By inspection — for circuits with only resistors and independent voltage sources, $\mathbf{RI}={\mathbf{V}}_s$ where:

• $R_{kk}$ = sum of resistances in mesh $k$
• $R_{kj}$ = negative of resistance shared between meshes $k$ and $j$
• $V_{s,k}$ = sum of voltage sources driving mesh $k$ in the assumed direction

Mesh is generally easier when there are few meshes relative to nodes, or when most sources are voltage sources.

When a current source is shared between two adjacent meshes, you can't write a standard KVL through it — the voltage across the source isn't known up front.

The supermesh technique: treat the two meshes plus the current source between them as one big 'supermesh', drawn around the outside *excluding* the shared current source. Write KVL around this supermesh boundary. Then add a constraint equation from the current source:

$$i_i-i_j=I_s$$

(sign per the source's arrow direction).

Procedure:

1. Identify any current source shared between two meshes.
2. For each such source, form a supermesh around the two meshes, excluding the source.
3. Write KVL for the supermesh.
4. Add the constraint equation $i_i-i_j=I_s$.
5. Write KVL normally for all non-supermesh meshes.

If the current source is between a mesh and the outside (so only one mesh touches it), that mesh's current is directly known ($i_k=I_s$) — no supermesh needed.

Both methods solve the same circuit and give the same answer. Which is faster depends on the network's geometry and source mix.

Prefer nodal when:

• The circuit has fewer nodes than meshes.
• Most sources are *current sources*.
• You need a *voltage* answer directly (saves the conversion).
• The circuit is non-planar (mesh analysis only works on planar circuits anyway).

Prefer mesh when:

• The circuit has fewer meshes than nodes.
• Most sources are *voltage sources*.
• You need a *current* answer directly.

Equation count comparison for a circuit with $b$ branches, $n$ nodes, $\ell =b-n+1$ meshes:

• Nodal: $n-1$ equations
• Mesh: $\ell =b-n+1$ equations

So if $n-1<b-n+1$, i.e. $b>2n-2$, mesh is bigger and nodal wins.

Practical advice: count both quickly before starting. Don't half-finish mesh because you forgot to check that nodal would have been three equations smaller.

For circuits restricted to resistors + independent sources, both nodal and mesh equations can be written down by inspection without going through the full KCL/KVL setup. This is much faster on exams.

Nodal by inspection — for $n-1$ non-reference nodes:

$$\mathbf{GV}={\mathbf{I}}_s$$

• $G_{kk}$ = sum of all conductances ($\frac{1}{R}$) connected to node $k$.
• $G_{kj}$ = negative of conductance directly connecting nodes $k$ and $j$ (0 if not connected).
• $I_{s,k}$ = sum of independent current sources flowing into node $k$.

Mesh by inspection — for $\ell$ meshes (all currents assigned clockwise):

$$\mathbf{RI}={\mathbf{V}}_s$$

• $R_{kk}$ = sum of all resistances in mesh $k$.
• $R_{kj}$ = negative of resistance shared between meshes $k$ and $j$.
• $V_{s,k}$ = algebraic sum of voltage sources around mesh $k$ in the assumed direction.

Both matrices are symmetric ($G_{kj}=G_{jk}$, $R_{kj}=R_{jk}$) — a useful sanity check.

Limitation: by-inspection rules don't apply to circuits with dependent sources or ideal voltage/current sources that violate the by-inspection assumptions (use supernodes / supermeshes for those).

Bipolar junction transistors (BJTs) in DC bias analysis are a natural application of nodal and mesh techniques. The BJT itself is nonlinear, but in DC analysis we use a piecewise linear model:

• Base-emitter: a fixed voltage drop $V_{BE}\approx 0.7$ V (silicon) when on.
• Collector current: $I_C=\beta I_B$ where $\beta$ (or $h_{FE}$) is the current gain (typically 50–300).
• Emitter current: $I_E=I_B+I_C=(\beta +1)I_B$.

Once you replace the transistor with these constraints, the surrounding network is purely linear and ordinary KVL/KCL analysis gives you the bias point ($V_C,V_B,V_E,I_C,I_B$).

Why this matters: every amplifier, every logic gate, every analog stage starts from a bias-point calculation. Mastering KCL/KVL with one or two transistors in the loop is the first real engineering application of the methods of analysis.